Device for scanning an image in successive lines, utilizing the electrical charge transfer, incorporating a line memory and a television camera incorporating such a device

ABSTRACT

A device for the electric scanning of luminous images. It includes a matrix of N lines and M columns of photosensitive points. A system incorporating a line memory of M points receives in parallel the electric charges supplied by the M points of the same line parasitic charge are removed by diodes. The system insures the injection of the same predetermined quantity of charges between each of the photosensitive points and the output of the device. An output shift register receives in parallel the charges supplied by the line memory and supplies in series a picture scanning electric signal. This device is particularly intended for use in a television camera.

BACKGROUND OF THE INVENTION

The invention relates to the electrical scanning of luminous images insuccessive lines forming frames, using a charge transfer deviceincorporating a line memory.

Various solid state devices scan an image and supply a television camerawith a video electrical signal. They differ in the way in which thephotosensitive zone is formed and in the system for reading and removingthe charges produced by the image.

Charge transfer devices perform these, as described, for example, bySEQUIN and TOMPSETT, in "Charge Transfer Devices", pp. 152 to 169. In"frame transfer" or "interline structure" organisations the lightradiation is received on charge transfer registers. The charge transferthen takes place over large areas, which is a disadvantage, since it isdifficult to obtain high efficiency levels for such large areas. CID's(charge injection devices), do not have these disadvantages, butgenerally require reinjection of the charges into the semiconductorsubstrate, resulting in noise and difficulties in connecting with thecapacitance values during and after reading.

There is also the question of compatibility between the time necessaryfor light integration and for charge transfer when the latter solutionis adopted e.g. with the sweep time of the television screen. A 625 linestandard, these times are generally about 52 μs for the display time ofa line and 12 μs for the line return time.

In order to meet these different requirements, the Applicant Company hasproposed a so-called "line transfer" structure, described in U.S. Pat.No. 4,430,672. This structure has a matrix of N lines×M photosensitivezones or points onto which an image to be scanned is projected andconverted into electric charges called signal charges; a memory of Mpoints, called the line memory, for successively receiving the signalcharges stored by each line; a device for removing the parasitic chargesassociated with the line memory; and a CCD-type (charge coupled device)shift register receiving in parallel the content of the line memory andsupplying in series the image scanning electric signal.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a picture scanning device of the linetransfer type, as described above, in which improvements have been madeto insure the storage of successive lines and the removal of parasiticcharges, in order to improve the processing of small signals and reducenoise.

The device according to the invention has many of elementaryphotosensitive zones, called points, formed on the same semiconductorsubstrate in accordance with N lines and M columns, which are isolatedfrom one another and form a matrix in which are created electricalcharges, called signal charges, as a function of the illuminationreceived; a charge transfer system with M columns incorporating a memoryof M points, called the line memory, formed in the same semiconductorsubstrate and receiving in parallel the signal charges supplied by the Mpoints of the same line; the line memory including a first grid (G₁),placed on the path of the charges and receiving a constant potential(V₁), which ensures the decoupling of this grid from the upstream partof the device; a parasitic charge removal device incorporating a manydiodes and draining the parasitic charges from each of the columns,which insures the injection of the same predefined quantity of chargesinto each of the points of the line memory; and an analog shift registerreceiving in parallel the charges supplied by the line memory andsupplying in series a picture scanning electric signal.

The invention also relates to a television camera incorporating such apicture scanning device.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in greater detail hereinafter relative tonon-limitative embodiments and the attached drawings, which show:

FIG. 1 is a block diagram of the general organisation of a line transferstructure.

FIG. 2 a plan view of a first embodiment of the device according to theinvention.

FIGS. 3 (a to h) a sectional view of the device of FIG. 2, illustratingthe potentials at different times.

FIGS. 4 (a to f) signals which can be applied to the device of FIG. 2.

FIG. 5 a plan view of a second embodiment of the device according to theinvention.

FIGS. 6 (a to h) a sectional view of the device of FIG. 5 illustratingthe potentials at different times.

FIGS. 7 (a to f) signals which can be applied to the device of FIG. 5.

FIG. 8 a plan view of a third embodiment of the device according to theinvention.

FIGS. 9 (a to i) a sectional view of the device of FIG. 8 illustratingthe potentials at different times.

FIGS. 10 (a to d) signals which can be applied to the device of FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the various drawings, the same references designate the sameelements.

FIG. 1 shows the general organisation of a line transfer structure, asdescribed in U.S. Pat. No. 4,430,672. This structure includes aphotosensitive zone 1, a line memory 2 and an analog output shiftregister 3.

The photosensitive zone 1 receives the luminous image to be scanned andconverts it into electrical charges, called signal charges. The term"luminous image", relates not only to the detection of visiblewavelengths, but also the surrounding wavelengths, particularly in theinfrared. The photosensitive zone has many elementary zones 15, whichare also called points, arranged in N lines, designated L₁, L₂ . . .L_(N) and M columns, designated C₁, C₂ . . . C_(M) and forming a matrix.The photosensitive points of the same line are interconnected andconnected to a control device 14, which enables successive addressing ofthe lines. This device has e.g. a MOS-type shift register. Thephotosensitive points 15 of the same column are connected to the sameconnection, subsequently called the column connection towards linememory 2.

Thus, in parallel, line memory 2 receives the signal charges produced ateach of the photosensitive points 15 of the same line and then transfersthem in parallel to register 3. A device for restoring the level of thecolumn connections (RAN connection in the drawing) and a device foreliminating parasitic charges (not shown in FIG. 1) are also associatedwith line memory 2.

Register 3 is an analog shift register supplying the informationreceived in parallel in the series mode. This information constitutesthe optical image scanning video signal received in photosensitivezone 1. The register is preferably of the charge transfer or CCD type.

The coordination of the different picture integration operations inphotosensitive zone 1, the transfer of lines into line memory 2 and thenthe transfer of signals into register 3 for the different lines areeffected in the following manner.

The integration of the image is permanently carried out over the entirephotosensitive matrix 1, except for the line addressed by register 14.During the line return time, the content of line memory 2 is transferredinto shift register 3, and the input of the line memory is then closed.During the following line time, the content of register 3 is removed inseries and the connection between line memory 2 and register 3 isinterrupted. During this time, in a first phase there is a levelrestoring of the reader of points 15 (RAN connection), connected to linememory 2; and in a second phase one of the lines L of zone 1 istransferred to line memory 2, with the selection (or addressing) of aline being insured by register 14.

The following stage corresponds to the line return time during which thecontent of line memory 2 is discharged into register 3, the latterhaving been entirely scanned during the preceding stage.

According to another embodiment, the selection of a line, its transferinto the line memory and then into the shift register takes placeentirely during the line return time, the line time being reserved forthe level restoring of the reader, which improves as it becomes longer,and for the series removal from the shift register.

FIG. 2 shows a plane view of a first embodiment of the device accordingto the invention. The connections coming from the M column C of thephotosensitive matrix (C_(i-1), C_(i), C_(i+1)), each lead to areceiving diode D₂, of the signal charges Q_(si) coming from the matrix.It is produced, for example, by doping a semiconductor substrate, whichis advantageously the same as that on which the photosensitive matrix 1is formed. Thus, the device has M charge transfer columns, delimited byinsulating barriers 42, corresponding respectively to the M columnconnections of the photosensitive matrix.

The diodes D are aligned and are adjacent on the underside to electrodeor grid G₁ in strip form, which forms a screen for the charges betweendiodes D₂ and the remainder of the device shown in FIG. 2, whichprevents parasitic charges from being transmitted on column connectionC. In charge transfer devices it is particularly important to provideprotection against parasitic charges, whose amplitude can vary from onepoint to another of the circuit as a function of the geometricalvariations of the elements, and which limit the dynamics of the signal.To this end, grid G₁ is connected to a constant potential V₁.

Following the screen grid G₁, there is a grid G₂ in the form of a stripparallel to G₁ and raised to a second potential V₂, this has thefunction of fixing the potential of the column connections.

There is then a grid G₄, whose function is to store the charges, and isin strip form having e.g. rectangular notches 24 between two columns andevery other column. In at least part of each of the notches 24, there isa diode D₅ having the function of removing the parasitic charges. Thediodes D₅ are connected to a periodic potential V_(D5).

It may be seen on FIG. 3 that grid G₂ is surrounded by two coplanargrids G₁ and G₄. So the width of grid G₂ is defined in a singlephotogravure operation by the distance between grids G₁ and G₄. A betterhomogeneity is thus obtained on the width of grid G₂ which can greatlybe reduced.

The parasitics due to a variable penetration of diodes D₂ under the gridG₂ for the different photosensitive points are eliminated. This variablepenetration produces variable transfer times for the charge signal ofeach diode D₂ towards the memory; moreover, it increases the rapidity ofthe charge signal transfer from D₁ and D₂ to the memory, because of thesmall width of G₂.

The device also has a grid G₅ in the form of a strip covering storagegrid G₄ with an insulating layer level with notches 24, so as to beadjacent to above diodes D₅. Grid G₅ receives a periodic potential V₅and makes it possible to control the access of the charges to diodes D₅.

Parallel to grid G₅ and slightly covering the lower part of diodes D₅there is a grid G₇ to which is applied a periodic potential V₇ making itpossible to control the access to shift register 3.

The insulating barriers 42 are interrupted level with the notches 24 orare terminated, if there is no notch, by an extension, e.g. in the formof a triangle 43. Diodes D₅ are surrounded by a U-shaped insulatingbarrier 44 in such a way that diode D₅ remains accessible to chargescoming from the diodes D₂ of each of the columns. In this way, twochannels per column are defined: a first channel CL₁ limited by aninsulating barrier 42, its extension 43 and a U-shaped branch 44 on theoutside; and a second channel CL₂ limited by the inside of the sameU-shaped branch 44 and the second insulating barrier 42 limiting thecolumn in question.

Register 3 is a C.C.D. register with two phases φ₁ and φ₂. It has twoseries of storage electrodes 31, 32 and two series of transferelectrodes 33, 34, all having a substantially rectangular shape andpositioned perpendicular to grids G₁ to G₇. Grids 31 are connected tothe periodic potential φ₁ and grids 32 to the periodic potential φ₂.Grids 33 and 34 are respectively placed between the grid pairs 32, 31and 31, 32 in the charge transfer direction on an extra thickness ofinsulant and are respectively connected to potentials φ₁ and φ₂.Moreover, the electrodes of register 3 are positioned in such a way thatelectrodes 31 originate on insulating barriers 43 or 44, electrodes 32being located in the extension of channel CL₁. The registers 3 isbounded at the bottom by a horizontal insulating barrier 44, in the sameway as the device is bounded at the top, also by an horizontalinsulating barrier 41.

In this embodiment, as in the following embodiments, the variousinsulating barriers described can be constructed in a known manner, e.g.by overdoping a substrate having the same type of conductivity as thelatter, or a localized extra-thickness of the insulating layer(generally oxide) covering the substrate. The latter solution ispossibly accompanied by an overdoping of the substrate formed beneaththe extra-thick insulation. The various electrodes can also be formed inknown manner using e.g. metal or polycrystalline silicon. Finally, toprevent the formation of interference charges, each diode and part ofthe adjacent grids is covered with a layer which is opaque to lightbeams, such as an aluminium layer.

FIG. 3a is a sectional view of the device of FIG. 2 and diagrams 3b to3h illustrate the surface potential in the semiconductor substrate atdifferent times, the surface potential being represented on these andthe following diagrams as increasing in the downward direction. Tofacilitate the understanding of the operation of the device, the diagramof FIG. 3a is a section made at different locations.

To the left of an axis XX is shown a photosensitive point of matrix 1.For example, it is constituted by a grid G_(L) formed by an electrodewith a photodetecting MOS capacitance raised to a periodic potentialV_(GL) and which slightly overlaps the following grid G_(E). This is ascreen for the charges, separating the actual photosensitive zone fromthe column connection and is raised to a constant potential V_(GE). Thescreen grid G_(E) is followed by reading diode D_(L) formed in thesubstrate, which constitutes the starting point for the columnconnection c_(i). In a variant not shown, the photosensitive point has asecond image detection zone, whose frequency sensitivity iscomplementary to the MOS capacitance realised e.g. by a photodiode.

To the right of axis XX is shown a section in the device of FIG. 2 alonga line AA passing through diode D₂, grid G₁, grid G₄ and the secondchannel CL₂. Grid G₄ is followed by grid G₅, which also slightlyoverlaps it, G₅ is followed by diode D₅. It can be seen that grid G₂slightly overlaps the surrounding grids G₁ and G₄. It is also possibleto see the column connections c_(i) connecting diodes D_(L) and D₂.

Following diode D₅, it is possible to see a section in the device ofFIG. 2 along a line BB along the first channel CL₁ and separated in FIG.3a from what precedes it by an axis YY. The section of the first channelstarts level with grid G₄ and continues up to an electrode 32 ofregister 3, G₄ and 32 being separated by grid G₇, which slightlyoverlaps them. It should be noted that, both in this and the followingembodiments, the operation of the device is compatible with a "volume"charge transfer into output register 3. As is known, the charge transferin the volume of the semiconductor substrate is faster than the surfacetransfer and its efficiency is better. Volume transfer differs fromsurface transfer mainly through the higher potentials applied and adoping of that part of the semiconductor substrate where there is atransfer having a conductivity type which is opposite to that of theremainder of the substrate.

The drawings show a volume transfer operation and consequently a"hatched" doped area, designated T.V., extending beneath the electrodesof register 3 up to half of grid G₇.

These different elements are preferably formed on the same semiconductorsubstrate 21, covered with a insulating layer which is not shown. Thevarious electrodes are separated, in the case where they overlap, by aninsulating layer, which, for reasons of clarity, also is not shown.

The various diagrams (a to e) of FIG. 4 show the evolution in time ofcontrol signals applied to the device of FIG. 3.

FIG. 4a represents the potential V_(GL), which is at a constant highlevel (V_(H)), except during a time interval T₄ to T₇ corresponding tothe time for the transfer of the charges accumulated in a consideredphotosensitive point to the line memory and then to register 3 of FIG. 2and which essentially corresponds to the line return time.

FIG. 4d represents potential V₄, which is at a constant high level(V_(H)), except between times T₃ and T₅ surrounding time T₄.

FIG. 4c represents the potential V₅, which is at a high level (V_(H)) upto time T₀, when it passes to an intermediate level (V_(I)) and remainsthere up to a time T₂, T₀ and T₂ being before time T₃. As from time T₂,V₅ remains at a low level V_(B) up to a time T₈, which is after time T₇,when it again rises to the high level V_(H).

FIG. 4d represents potential V_(D5), which is at a constant high level(V_(H)) , except between time T₀ and a time T₁ between T₀ and T₂ duringwhich it is at a low level (V_(B)).

FIG. 4e represents potential V₇, which is at a constant low level,except between time T₆, which precedes time T₇, and T₇, during which itis at a high level (V_(H)).

In FIG. 3b, at a time t_(o) between time T₀ and T₁, diode D₅ is at lowlevel permitting the injection of charges beneath grid G₄. Thisinjection is limited by a constant potential V₂ applied to grid G₂,which implies that the low level of V_(D5) exceeds potential V₂. Thus,it would appear that grid G₂ fixes the potential level of the columnconnections c_(i). Moreover, to the left of line XX, a signal chargequantity Q_(si) is present beneath grid G_(L) (hatched area).

The diagram of FIG. 3c shows the potentials at a time t₁ between T₁ andT₂. At this time, potential V_(D5) is at high level and therefore acharge quantity Q₀ is isolated beneath grid G₄ (hatched area) bypotentials V₂ and V₅ respectively applied to grids G₂ and G₅. Thischarge quantity Q₀ is dependent on the potential V₁, which is thenapplied beneath grid G₅, potential V₂ being assumed lower than V_(I).

At a time t₂ between T₃ and T₄, voltages V₄ and V₅ are returned to lowlevel, which has the effect of transferring the charge quantity Q₀ todiodes D₂ and, via connections c_(i), to diodes D_(L). This isrepresented by an arrow 51 on the part of diagram 3d between lines XXand YY.

At a subsequent time t₃, between T₄ and T₅, the potential applied togrid G_(L) of the MOS capacitance of the photosensitive zone is broughtto a low level, which has the effect of transferring charge quantityQ_(si) to diodes D_(L) (arrow 52 in the left-hand part of FIG. 3d).

Diagram 3e represents the situation at a time t₄, between times T₅ andT₆. During this time, the potential applied to grid G₄ is raised to ahigh level, which makes it possible to transfer (arrow 53) charges Q₀+Q_(si) beneath grid G₄ in two channels, which is illustrated to theright and left of axis YY.

Diagram 3f represents the situation at a time t₅ between T₆ and T₇during which the potentials of channel CL₂ are unchanged, while thepotential of grid G₇ placed on channel CL₁ rises enabling the transfer(arrow 54) of the charges Q₀ +Q_(si) present beneath grid G₄ to shiftregister 3, materialised by one of its electrodes 32. Thus, the knowncharge quantity Q₀ is effectively transferred into register 3 at thesame time as signal charge Q_(si).

Generally, it is possible to avoid the transfer of the charge Q₀ intoregister 3, in which case only signal charge Q_(si) is transferred. Thismakes it possible to eliminate the so-called spatial noise on Q₀ fromone column to the next, the noise being due to variations in the changescaused by variations in the oxide thickness covering the substrate,variations in the threshold voltages, etc. This can be brought about byraising grid G₇ to an intermediate potential V₁, represented in diagram4f and whose amplitude is between V_(B) and V_(H) during times T₆ to T₇.The value V_(I) of this intermediate potential is advantageously equalto the intermediate potential applied to grid G₅ between times T₀ andT₂. In this way, an operation described by diagram 3g is obtained, whereit is possible to see that the potential applied to grid G₇ is such thatonly the signal charge Q_(si) (arrow 55) can be transferred from grid G₄to electrode 32 above grid G₇, charge Q₀ remaining beneath grid G₄. Itshould be noted that in this variant, the phase corresponding to diagram3b can be eliminated. This stage is an injection stage of Q₀ into thedevice, which is no longer necessary because this charge is no longereliminated.

It is essential that the charge signal transfer Q_(si) from diodes D₂under grid G₂ then under grid G₄ includes the addition of a chargequantity Q_(o), the capacity of the diodes D₂ being quite important. Butthe transfer of the charge signal Q_(si) to the reading register doesn'tnecessitate the addition of the charge quantity Q_(O), the capacity ofthe grid G₄ being small, of the same dimension as the capacity of theregister.

At a time t₆, following time T₈ and at a random point during the linetime, the potential applied to grid G₅ being raised to the high levelV_(H), there is an elimination of any parasitic charge (Q_(B)) from acolumn connection, by channel CL₂ to diode D₅. These parasitic chargesresult e.g. from overilluminated points of the photosensitive matrix.

On referring to the variant described by diagrams 4f and 3g, it isnecessary that at time t₆, the potential applied to grid G₅ is equal tothe intermediate level V₁ and not to V_(H) in order to ensure that onlycharge Q₀ is beneath grid G₄ and to eliminate possible parasitic chargesby D₅.

In this latter variant, the residual spatial noise can only be due tovariations of the threshold, doping or insulation thickness betweengrids G₇ and G₅, which is minimal in practice, bearing in mind thegeometrical proximity of these grids.

Thus, this structure permits the injection of a predetermined quantityof Q₀, first beneath the storage grid G₄ and then onto diodes D_(L) andD₂ establishing the connection between photosensitive matrix and theline memory, in order to improve the transfer of signal charges Q_(si).This quantity of charges Q₀ is consequently injected by using thestructure of the line memory and the parasitic charge eliminationdevice, so that no auxiliary device is required.

Moreover, in this embodiment, each parasitic charge removal diode D₅ iscommon to both columns making it possible either to increase the storagecapacity of the line memory (more extensive grid G₄) or to permit asmaller horizontal spacing and consequently a reduced overall size ofthe device.

FIG. 5 is a plan view of a second embodiment of the invention, where thegeneration of the charge quantity Q₀ is completely free from spatialnoise.

In FIG. 5, it is possible to see diodes D₂, grid G₁, grid G₂ and G₄,which in this case has a notch 25 level with each of the columns and, asbefore, each of these notches contains a diode D₅. Grids G₅ and G₇ arearranged parallel to the other grids on either side of diodes D₅.Perpendicular to these, it is possible to see the electrodes 31 to 34 ofregister 3.

Once again, there are vertical insulating barriers 42 between thecolumns which extend up to electrodes 34 of register 3. Moreover, eachof the columns is vertically subdivided by an insulating barrier 45,defining to its left a first channel CL₁ extending from grid G₄ to anelectrode 32, and to its right a second channel CL₂ containing diode D₅,which then extends between barriers 45 and 42, and finally a thirdchannel CL₃ extending from electrode 31 of register 3 to diode D₅, i.e.opposite to channel CL₂.

To the left of axis ZZ, FIG. 6a shows a section along a closed line CCformed as from diode D₅ around the insulating barrier 45 of FIG. 5; tothe right of axis ZZ there is a section along a line DD from grid G₄ todiode D₂, these two sections being joined to make it easier to explainthe operation of the device of FIG. 5.

In succession starting from the left, FIG. 6 shows channel CL₂represented by diode D₅, grid G₅ slightly overlapping the following gridG₄, the latter being common to channel CL₂ and CL₁, then channel CL₁represented by grid 32 separated from grid G₄ by grid G₇, which slightlyoverlaps both of them. Grid 31 is separated from grid 32 by grid 33,which slightly overlaps them and which forms the separation betweenchannels CL₁ and CL₃, then channel CL₃ constituted by grid G₇ and diodeD₅. To the right of line ZZ are successively provided grid G₄, grid G₁separated from G₄ by grid G₂ which slightly overlaps them, followed bydiode D₂, which receives column connections c_(i).

As before, there is a doping zone extending from grid G₇ to electrodes31, 32 and 33 of register 3 corresponding to the volume transfer type ofoperation of the register.

The various diagrams (a to f) of FIG. 7 show the evolution in time ofthe various control signals applied to the device of FIG. 5. Thesecontrol signals are periodic potentials, whose amplitude varies betweena low level V_(B) for all the diagrams and a high level V_(H) for allthe diagrams, but these different potentials are not necessarily equal.

Diagram 7a represents potential V₅ which is at a high level, except froma time T₂ and up to a time T₈, the time between T₂ and T₈ beingessentially that of the line return.

Diagram 7b represents potential V_(D5) which is at a high level, exceptbetween times T₁ and T₃ surrounding time T₂, when it is at a low level.

Diagram 7c represents potential V₇ which is at a low level up to a timeT₄ after time T₃ at which it passes to a high level, up to a subsequenttime T₅ when it again passes to a low level, up to a subsequent time T₆when it again passes to a high level, up to T₈ when it again passes to alow level.

Diagram 7d represents potential φ₂, which is a square wave signal ofcycle or period T up to a time T₀ preceding time T₁ at which it passesto a high level up to time T₅. It then passes to a low level, which itmaintains up to a time T₆, when it passes to a high level up to a timeT₈, and then it again becomes a square wave signal of the same period asbefore.

Diagram 7e shows potential φ₁, which is complementary to potential φ₂.

Diagram 7f represents potential V₄ which is at a high level up to timeT₅, at which it passes to a low level up to time T₇ between T₆ and T₈,when it again passes to a high level.

FIG. 6b shows the surface potential in the semiconductor level with FIG.6a at a time t₀ between T₁ and T₂. For reasons of clarity in this andthe following diagrams, each of them shows the surface of thesemiconductor substrate 22. At this time t₀, potential V_(D5) applied todiode D₅ is at a low level, but potential V₅ applied to grid G₅ is at ahigh level. As a result, it is possible for the charges to invade thearea located beneath grid G₄, but this invasion (hatched area) islimited by grid G₇ raised to potential V₇, which is at low level.

FIG. 6c shows the surface potential at a time t₁ between T₂ and T₃. Theonly change from the preceding drawing is the passage of potential V₅ tolow level, which isolates a charge quantity Q'₀ beneath grid G₄.

Diagram 6d represents the surface potential at a time t₂ between timesT₄ and T₅. The difference from the previous diagram is that potential V₇applied to grid G₇ passes to a high level, which has the effect ofsubdividing the charge quantity Q'₀ beneath electrode G₄ into a quantityQ₀ remaining beneath this grid as a function of the potential levelV_(H) of V₇, and defined by the surface potential beneath G₇ out of thedoped zone T.V., and a residual charge quantity Q_(r), which istransferred beneath grid 32 to which is applied potential φ₂, which atthis instant is at high level.

Diagram 6e shows the surface potential at time t₃ between times T₅ andT₆. During this period, potential φ₂ is brought to low level, which hasthe effect of transferring charge Q_(r) beneath electrode 31, potentialφ₁ then being at high level. Moreover, as the potential V₄ of grid G₄ isat low level, the charge quantity Q₀ is transferred to diode D₂ and tocolumn connections c_(i), which is shown to the right of axis ZZ,reference again being made to the fact that potentials V₁ and V₂ areconstant and higher than the low level of V₄. The potential V₇ appliedto grid G₇ is at a low level during this time, so that access toregister 3 is impossible.

Moreover, at time t₃ the presence of charges Q_(si) are shown on thecolumn connection c_(i). The transfer of Q_(si) from a photosensitivepoint of column c_(i) takes place in the manner described relative toFIG. 3d. This transfer can take place at any time before t₅ (FIG. 6g)but it is preferable for Q₀ to be transferred before or at the same timeas Q_(si) on column connection c_(i).

Diagram 6f represents the surface potential at a time t₄ between timesT₆ and T₇. During this period, the passage of potential V₇ to a highlevel makes it possible to remove the charges Q_(r), previously beneathelectrode 31, to diode D₅ via channel 3. During this same period, φ₂returns to a high level and φ₁ to low level.

Diagram 6g represents the surface potential at a time t₅ between T₇ andT₈. During this period, the potential applied to grid G₄ returns to highlevel, so that the charge quantity Q₀ +Q_(si) present on connectionc_(i) (right-hand part of the drawing) is transferred beneath grid G₄and then partly beneath electrode 32, while charge quantity Q₀ is heldback by the potential barrier beneath grid G₇ in the same way as at timet₂. In this way, only Q_(si) is transferred beneath electrode 32 ofoutput register 3.

Diagram 6h represents the surface potential at a time t₆ following timeT₈, potentials φ₁ and φ₂ then being respectively at high level and atlow level. During this time, potential V₄ applied to grid G₄ is at highlevel, which makes it possible to eliminate all the parasitic chargesQ_(p) present on column connection c_(i), the charges being transferredover grid G₂ to grid G₄ and from grid G₄ to the parasitic chargeelimination diode D₅, grid G₅ then being raised to a high levelpotential V₅. Throughout this period, charge Q_(si) is transferredbeneath the following electrode 31 of output register 3.

This second embodiment described in FIGS. 5 and 7 consequently permitsthe generation of charge Q₀ at the line memory in a completely spatialnoise-free manner, because it is determined by the potential applied togrid G₇ and then stopped by the same grid during the transfer of thesignal charges Q_(si) to output register 3. The residual charges Q_(r)or parasitic charges Q_(p) are eliminated before any scan by diode D₅ bymeans of channel CL₂ or channel CL₃ and in this case via register 3.

FIG. 8 shows a third embodiment of the device according to theinvention, which also makes it possible to eliminate the spatial noisein the generation of charge Q₀ by means of a two-stage line memorystructure. Here the two functions previously fulfilled by storage gridG₄ are realised by two separate grids.

FIG. 8 shows a structure identical to that of FIG. 2, one diode D₂ percolumn receiving the column connection c_(i-1), c_(i) and c_(i+1),followed by grid G₁, which is itself followed by grid G₂, respectivelyraised to constant potentials V₁ and V₂. Grid G₄ is now replaced by afirst grid G₄₁ in the form of a strip and raised to a periodic potentialV₄₁. Its function is to maintain charge Q₀, whose value is determined bya grid G3 which follows G₄₁ and raised to a periodic potential V₃. GridG₃ is followed by a second grid such as G₄, designated in this case G₄₂and having notches 26 identical to the notches 24 of FIG. 2 in which areformed diodes D₅. It has the function of branching charges betweenregister 3 and the parasitic charge elimination diodes D₅. G₄₂ is raisedto a periodic potential, V₄₁ and the diodes D₅ are raised to a constantpotential V_(D5).

The columns are separated from one another, as before, by an insulationbarrier 42 and diodes D₅, surrounded by U-shaped insulation barriers 44arranged in such a way that one diode D₅ is common to two columns andthe flow of charges transferred into a column is divided into twochannels CL₁ and CL₂ at grid G₅, which is adjacent to diodes D₅, asbefore. The device also has grid G₇, raised to potential V₇, and outputregister 3, constructed in the same way as hitherto. Insulation barriers42 either terminate before diodes D₅ or beneath grid G₇ by an e.g.square extension 46, in such a way that the charges transferred intochannel CL₁ can only be transferred towards electrode 32.

FIG. 9a represents a sectional view of the device of FIG. 8 along with aline EE extending from diode D₂ to diode D₅, then from diode D₅ to anelectrode 32 of the reading register.

Thus, in FIG. 9a and starting from the left, it is possible to see diodeD₂ receiving column connection c_(i), grid G₁, grid G₄₁, grid G₂ betweengrids G₁ and G₄₁ and slightly overlapping the latter, grid G₄₂, grid G₃placed between grids G₄₁ and G₄₂ and slightly overlapping them, grid G₅slightly overlapping the latter and diode D₅, then grid G₅ and grid G₄₂,and then grid G₇ and grid 32 of the reading register 3.

The various diagrams (a to d) of FIG. 10 represent the control signalswhich can be used in the device of FIG. 8. These control signals areperiodic potentials, whose amplitude varies between a high level and alow level, designated V_(H) and V_(B) respectively for all the diagrams.However, these different potentials are not necessarily equal to oneanother or equal to the potentials of the previous drawings.

Diagram 10a shows potentials V₄₁ and V₄₂ applied to grids G₄₁ and G₄₂.It is at low level, except at times t₁, t₂, t₃ and t₆, t₇, t₈, when itis at high level.

Diagram 10b represents potentials V₃ and V₂ applied to grids G₃ and G₂ ;it is at high level during times t₂ and t₇.

Diagram 10c represents potential V₅ applied to grid G₅. It is at lowlevel V_(B), except during times t₁, t₂, t₃ and t₄.

Diagram 10d represents potential V₇ applied to grid G₇. It is at lowlevel except during times t₆, t₇, t₈ and t₉, when it is at high level.

Diagrams 9b to 9i represent the potential on the surface of thesemiconductor substrate, at different times and increasing in thedownward direction.

FIG. 9b represents the surface potential during time t₁. Grid G₂ is at alow level V_(B) and isolates the photosensitive zone from the remainderof the device. On the columns, there is the training charge quantityQ_(o) and a charge quantity Q_(B) due to a possible overlighting.

FIG. 9c represents the surface potential during time t₂. Grids G₂ and G₃are at a high level. The charge quantity Q_(o) +Q_(B) is transferred inthe line memory. Charge quantity Q_(o) fullfils the potential wellbeneath grid G₄₁ and charge quantity Q_(B) is transferred under gridsG₄₂.

FIG. 9d represents the surface potential during time t₃. Grid G₂ is at alow level. The photosensitive zone is isolated from the remainder of thedevice. Grid G₃ is at a low level separating the grids G₄₁ and G₄₂.

FIG. 9e represents the surface potential during time t₄. Grids G₄₁ andG₄₂ are at a low level. Charge quantity Q_(o) is transferred fromcolumns and charge quantity Q_(B) is evacuated by drain D₅.

FIG. 9f represents the surface potential during times t₅ and t₆.

At time t₅, grid G₅ is at a low level and isolates the line memory fromthe drain D₅. Moreover a clock signal, not shown on the figure, producesthe arrival of the charge quantity Q_(S) on the column connections.There is then on the columns connections Q_(o) +Q_(S).

At time t₆, grid G₇ and grids G₄₁ and G₄₂ are at a high level.

FIG. 9g represents the surface potential during time t₇. Grid G₃ is at ahigh level and there is communication between grids G₄₁ and G₄₂. Grid G₂is at a high level and there is transfer from charge quantity Q_(o)+Q_(S) from the column connections in the line memory. The chargequantity Q_(o) is blocked under grid G₄₁ and the signal charge quantityQ_(S) is transferred under grid G₄₂.

FIG. 9h represents the surface potential during time t₈. Grid G₂ is at alow level; so is grid G₃.

FIG. 9i represents the surface potential during time t₉ : Grids G₄₁ andG₄₂ are at a low level and there is transfer of the signal chargequantity Q_(S) in the reading register 32 and transfer of the chargequantity Q_(o) on the columns. The transfer of Q_(o) on the columns attime t₉ explains that at time t₁ the charge quantity Q_(o) +Q_(B) is onthe columns.

In the embodiments of FIGS. 5 and 8, the generation of the chargequantity Q_(o) in the line memory is quite independent from the spatialnoise because this charge is created then stopped by the same gridreceiving the same potential. For FIGS. 6d and g, it is the grid G₇ atthe potential V₇. For FIG. 9d and g, it is the grid G₃ at potential V₃.

In the embodiment of FIG. 8, the transfer from the columns to the linememory of the signal charge quantity Q_(S) and of the charge quantityQ_(B) constituted by overlighting charges is made by adding the trainingcharge Q_(o), independent from the spatial noise, to these chargequantities.

In the embodiments of FIGS. 2 and 5, it would be also possible to addthe charge quantity Q_(o) to the charge quantities Q_(S) and Q_(B) whenthere is transfer of the charges from the columns to the line memory.

In the operating mode of FIG. 8, the grid G₂ is no longer at a constantpotential as it was in the operating modes of FIGS. 2 and 5.

Where G₂ is at a constant potential, after signal charges Q_(S) havebeen transferred from D₂ to G₄, the surface potential at diode D₂ isequal to that of grid G₂. New signal charges will arrive under D₂ onlyat the time of the next line return. During the time interval betweenthese two arrivals of charges, there is a leakage current which,although the MOS transistor formed by diode D₂, grid G₂ and thepotential well under G₃ is blocked, evacuates some charges from D₂ toG₄. This leakage current is known as subthreshold current. The surfacepotential at D₂ increases slightly from ΔV compared with that of G₂.When the signal charges of the following line are transferred on thecolumn, they must first fill the potential "pocket" ΔV before chargeQ_(si) can be transferred to G₄. A quantity of charges Q_(p) =C₁ ·ΔV,where C₁ is the column capacity, is blocked on the column and only thedifference Q_(si) -Q_(P) is transferred, so there is a diminution of theuseful signal. Sometimes, there is even Q_(P) >Q_(si). In the operatingmode of FIG. 8, the leakage current is delated by applying to grid G₂not a continuous voltage V₂, but a periodic signal V₂ havingperiodically a high and a low level.

So, during the line time, the signal V₂ is at a low level. There is alarge potential barrier between the potential at D₂ and the potentialunder grid G₂. The leakage current is then negligible.

During the line return time when charges have to be transferred from thecolumns to G₄, the signal V₂ is at a high level. The potential barrierbecomes zero, so the potential at D₂ equals that of grid G₂.

This pulse on G₂ occurs each time there is transfer from the columns tothe line memory, of reading signal charges or of overlighting chargesQ_(B) at the end of the line time, for example.

The amplitude of the pulse on G₂ is approximately 1V to efficaciouslyreduce the leakage current, and it is approximately 10 to 15 Volts forthe different control signals referred to hereinbefore.

Grid G₁ is quite important in this mode of operating. It deletes theparasitic coupling between G₂ and D₂ which would have maintained thepotential barrier when there is a pulse on G₂. The diode D₂, whithoutthe grid G₁, whould follow the potential of G₂ because of its couplingcapacity with G₂.

In the embodiments of FIGS. 2 and 5, it is also possible to maintain thegrid G₁ at a constant potential and to apply to grid G₂ a periodicsignal so as to maintain it at a low level, except when there istransfer of charges to the line memory.

The above description has been given relative to a non-limitativeembodiment. Thus, the relative positioning of grids G₁, G₅ and G₇ ofdiodes D₂ and D₅, as well as their dimensions, have no particularfunction and instead only devolve from the technological constructionprocedure. In the same way, the shape of the insulation barriers 43 and46 are of a random nature, which also applies with respect to the shapeof notches 24 and 26.

What is claimed is:
 1. An area image sensory device comprising:(a) asemiconductor substrate, (b) a plurality of elementary photosensitiveareas formed on said substrate and separated from one another and formedin a matrix of N lines and M columns, and in said areas electricalcharge signals are produced proportional to received illumination of animage; (c) a charge transfer device formed on said substrate having linememory means with M areas for receiving in parallel the electricalcharge signals from M photosensitive areas which are all in a same lineand periodically supplying said charge signals to an output; said linememory means having(i) first grid means (G₁) adapted to be connected toa constant potential (V₁) and located between the matrix and said areasof the memory for insuring decoupling between said areas of the matrixand the charge transfer device, (ii) at least one charge storage gridadapted to be connected to a periodic amplitude alternating potentialfor maintaining the electrical charge signals, (iii) supplementary gridmeans adjacent to said storage grid for receiving a periodic amplitudealternating potential, (iv) parasitic charge removal means having aplurality of removal diodes for draining parasitic charges from each ofsaid columns, and (v) control grid means for receiving a periodicamplitude alternating potential and for controlling access to saidremoval diodes, a training charge (Qo) being maintained beneath saidstorage grid during said parasitic charge drawing and during receivingsaid electrical charge signals only by a potential barrier beneath saidsupplementary grid means being caused by said periodic potentialreceived by said grid means reaching a predetermined amplitude; and (d)analog shift register means for receiving in parallel said chargesignals supplied by said line memory and for supplying in series anoutput picture scanning signal.
 2. A device according to claim 1 whereinthe line memory means further comprises a further storage grid locatedbetween said first grid means and said one charge storage grid andseparated from said one charge storage grid by a supplementary grid,said two storage grids means storing the electrical charge signal.
 3. Adevice according to claim 1 wherein the line memory means furthercomprises second grid means located between the storage grid and saidfirst grid means for fixing a potential at column connections betweensaid row memory and said matrix and insuring charge transfer from thematrix to the line memory means.
 4. A device according to claim 3wherein said second grid means is adapted to be connected to a periodicamplitude alternating potential for authorizing a charge transfer ofelectrical charge signals from said M photosensitive areas to said linememory.
 5. A device according to claim 3 wherein said second grid means(G₂) is adapted to be raised to a rising potential for transferringelectrical charge signals (QS) coming from an overlighting (QB) fromsaid M photosensitive areas and the column connections to the linememory means, a charge quantity (QO) being added to the electricalcharge signals when there is a transfer from the column connections tothe line memory means.
 6. A device according to claim 2 wherein the linememory also comprises second grid means located between the storage gridand said first grid means for fixing a potential at column connectionsbetween said matrix and said line memory and insuring charge transferfrom the matrix to the line memory means.
 7. A device according to claim6 wherein the second grid means is adapted to be raised to a periodicamplitude alternating potential for authorizing a charge transfer fromsaid column connection to said line memory means.
 8. A device accordingto claim 6 wherein said second grid means is adapted to be raised to arising potential for transferring signal charges (QS) coming from anoverlighting (QB) from said column connections to said line memory; acharge quantity (QO) being added to the signal charges and to theoverlighting charges during transfer from said column connections tosaid line memory means.
 9. A device according to claim 1 wherein saidstorage grid has notches in which are placed said charge removal diodes.10. A device according to claim 9 wherein said notches are positionedwith each charge removal diode being common to two channels.
 11. Adevice according to claim 9 wherein said storage grid has one notch perchannel.
 12. A device according to claim 1 further comprising connectingmeans for supplying in parallel said electrical charge signals producedin M elementary photosensitive areas of the same line of the matrix,successively for N lines; said connecting means having a plurality ofreading diodes and reception diodes, said reading diodes being arrangedin columns between said elementary selective areas and M receptiondiodes located at an input to said charge transfer device from saidmatrix; each of said reading diodes being electrically coupled to acorresponding reception diode.
 13. A device according to claim 12wherein each of said elementary sensitive areas of said matrix comprisesa MOS capacitance having a first charge election zone including a grid,common to capacitances of a same line, and a second charge election zoneelectrically coupled to said capacitances, and means for forming ascreen for the electrical charge signals positioned between each of saidelementary sensitive areas and said connecting means, said screen meanshaving a plurality of grids adapted to be raised to a constant potentialand arranged in columns between said reading diode and saidphotosensitive points.
 14. A device according to claim 1 wherein saidperiodic amplitude alternating potentials are such that the injection ofthe previously defined charge quantity is brought about beneath thestorage grid by the charge transfer removal diode.
 15. A deviceaccording to claim 14 wherein the periodic potentials are such thatcharges are injected beneath the storage grid by the charge removaldiode, the quantity of charges beneath the storage grid being brought toa previously defined charge quantity by means of a supplementary gridcontrolling the access to the shift register, the residual chargequantity being eliminated on the charge removal diode after transit inthe shift register.
 16. A device according to claim 2 wherein theelectrical charge signal is maintained beneath the storage grid at alltimes except during a transfer of the electrical charge signal to theline memory.
 17. A device according to claim 12 further comprising ascreen which is opaque to received illumination and which screen coversthose portions of the device having the diodes.
 18. A device accordingto claim 1 wherein an insulating layer covers semiconductor substrate.19. A device according to claim 18 wherein said insulating layercomprises an overdoping from the semiconductor substrate.